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cy8c20224, cy8c20324 cy8c20424, cy8c20524 capsense ? psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-41947 rev. *l revised june 15, 2012 capsense ? psoc ? programmable system-on-chip features low power, configurable capsense ? ? configurable capacitive sensing elements ? operating voltage ? operating voltage: 2.4 v to 5.25 v ? low operating current ? active 1.5 ma (at 3.0 v, 12 mhz) ? sleep 2.8 a (at 3.3 v) ? supports up to 25 capacitive buttons ? supports one slider ? up to 10 cm proximity sensing ? supports up to 28 general-purpose i/o (gpio) pins ? drive leds and other outputs ? configurable led behavior (fading, strobing) ? led color mixing (rbg leds) ? pull-up, high z, open-drain, and cmos drive modes on all gpios ? internal 5.0% 6 or12 mhz main oscillator ? internal low-speed oscillator at 32 khz ? low external component count ? no external crystal or oscillator components ? no external voltage regulator required high-performance capsense ? ultra fast scan speed ?1 khz (nominal) ? reliable finger detection through 5 mm thick acrylic ? excellent emi and ac noise immunity industry best flexibility ? 8 kb flash program storage 50 ,000 erase and write cycles ? 512-bytes sram data storage ? bootloader for ease of field reprogramming ? partial flash updates ? flexible flash protection modes ? interrupt controller ? in-system serial programming (issp) ? free complete development tool (psoc designer?) ? full-featured, in-circuit emulator and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory additional system resources ? configurable communication speeds ? i 2 c slave ? spi master and spi slave ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit logic block diagram sram 512 bytes system bus interrupt controller 6/12 mhz internal main oscillator global analog interconnect psoc core cpu core (m8c) srom flash 8k system resources analog system analog ref. i2c slave/spi master-slave por and lvd system resets port 1 port 0 sleep and watchdog ana l og mu x port 3 port 2 capsense basic block 3v ldo
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 2 of 41 contents psoc ? functional overview ............................................ 3 psoc core .................................................................. 3 capsense analog system .......................................... 3 additional system resources ..................................... 4 getting started .................................................................. 4 application notes ........................................................ 4 development kits ........................................................ 4 training ....................................................................... 4 cypros consultants .................................................... 4 solutions library .......................................................... 4 technical support ....................................................... 4 development tools .......................................................... 5 psoc designer software subsyst ems .......... .............. 5 designing with psoc designer ....................................... 6 select user modules ................................................... 6 configure user modules .............................................. 6 organize and connect .............. .............. ........... ......... 6 generate, verify, and debug ....................................... 6 pinouts .............................................................................. 7 16-pin part pinout ........................................................ 7 24-pin part pinout ........................................................ 8 28-pin part pinout ........................................................ 9 32-pin part pinout ...................................................... 10 48-pin ocd part pinout ............................................. 12 electrical specifications ................................................ 14 absolute maximum ratings .......................................... 14 operating temperature .................................................. 14 dc electrical characteristics ........................................ 15 ac electrical characteristics ........................................ 19 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 packaging dimensions .................................................. 27 thermal impedances ................................................ 30 solder reflow specifications ..................................... 30 development tool selection .. .............. .............. ........... 31 software .................................................................... 31 development kits ...................................................... 31 evaluation tools ........................................................ 31 device programmers ............. .................................... 32 accessories (emulation and programming) .............. 32 acronyms ........................................................................ 33 acronyms used ......................................................... 33 reference documents .................................................... 33 document conventions ................................................. 34 units of measure ....................................................... 34 numeric conventions ............ .................................... 34 glossary .......................................................................... 34 document history page ................................................. 39 sales, solutions, and legal information ...................... 41 worldwide sales and design s upport ......... .............. 41 products .................................................................... 41 psoc solutions ......................................................... 41
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 3 of 41 psoc ? functional overview the psoc family consists of many programmable system-on-chips with on-chip co ntroller devices. these devices are designed to replace multip le traditional mcu based system components with one, low cost single chip programmable component. a psoc device includes configurable analog and digital blocks, and programmable interconnect. this architecture enables the user to create custom ized peripheral configurations, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the psoc architecture for this device family is comprised of three main areas: core, system resources, and capsense analog system. a common, versatile bus enables connection between i/o and th e analog system. each cy8c20x24 psoc device includes a dedicated capsense block that provides sensing and scanning control circ uitry for capacitive sensing applications. depending on the psoc package, up to 28 gpios are also included. the gpios provide access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (imo) and internal low-s peed oscillator (ilo). the cpu core, called the m8c, is a powerful processor with speeds up to 12 mhz. the m8c is a 2-mips, 8-bit harvard-architecture microprocessor. system resources provide additional capability, such as a configurable i 2 c slave or spi master-slave communication interface and various system re sets supported by the m8c. the analog system is composed of the capsense psoc block and an internal 1.8-v analog reference. together, they support capacitive sensing of up to 28 inputs. capsense analog system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins are completed quickly and easily across multiple ports. figure 1. analog system block diagram analog multiplexer system the analog mux bus connects to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications such as touch sensing. the analog multiplexer system in t he cy8c20x24 device family is optimized for basic capsense functionality. it supports sensing of capsense buttons, proximity sensors, and a single slider. other multiplexer applications include: capacitive slider interface. chip-wide mux that enables analog input from any i/o pin. crosspoint connection between any i/o pin combinations. when designing capacitive sensing applications, refer to the latest signal to noise signal level requirements application notes, which are found in http://www.cypress.com > design resources > application notes. in genera l, and unless otherwise noted in the relevant application notes, the minimum signal-to-noise ratio (snr) requirement for capsen se applications is 5:1. id ac reference buffer vr cinternal analog global bus cap sense counters comparator mux mux refs capsense clock select relaxation oscillator (ro) csclk imo
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 4 of 41 typical application figure 2 illustrates a typical application: capsense multimedia keys for a notebook computer with a slider, four buttons, and four leds. figure 2. capsense multimedia button-board application additional system resources system resources, some of whic h are previously listed, provide additional capability useful to complete systems. additional resources include low voltage detection (lvd) and power on reset (por). brief statements describing the merits of each system resource follow. the i 2 c slave and spi master-slave module provides 50, 100, or 400 khz communication over two wires. spi communication over three or four wires runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). lvd interrupts signal the application of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal 1.8-v reference provides an absolute reference for capacitive sensing. the 5 v maximum input, 3 v fixed output, low dropout regulator (ldo) provides regulation for i/os. a register controlled bypass mode enables the user to disable the ldo. getting started this datasheet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assis- tance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 5 of 41 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (dacs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy deve lopment of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for a given application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu regist ers, set and clear breakpoints, and provide program run, halt , and step control. the debugger also allows you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. th is system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24-mhz) operation.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 6 of 41 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of use r-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter va lues directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module data sheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to -breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 7 of 41 pinouts this section describes, lists, and illustrat es the cy8c20224, cy8c20324, cy8c20424, a nd cy8c20524 psoc device pins and pinout configurations. the cy8c20x24 psoc device is available in a variety of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o and connection to the common analog bus. however, v ss , v dd , and xres are not capable of digital i/o. 16-pin part pinout figure 3. cy8c20224 16-pin psoc device qfn (top view ) ai, p2[5] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai vdd p0[4], ai clk, i2c scl, spi mosi p1[1] ai, data, i2c sda, p1[0] p1[2], ai ai, p2[1] p1[4], ai, extclk xres p0[1], ai vss 12 5 6 7 8 table 1. 16-pin part pinout (col) pin no. digital analog name description 1 i/o i p2[5] 2 i/o i p2[1] 3 i oh i p1[7] i 2 c scl, spi ss 4 i oh i p1[5] i 2 c sda, spi miso 5 i oh i p1[3] spi clk 6 i oh i p1[1] clk [1] , i 2 c scl, spi mosi 7 power v ss ground connection 8 i oh i p1[0] data [1] , i 2 c sda 9 i oh i p1[2] 10 i oh i p1[4] optional external clock input (extclk) 11 input xres active high external reset with internal pull-down 12 i/o i p0[4] 13 power v dd supply voltage 14 i/o i p0[7] 15 i/o i p0[3] integrating input 16 i/o i p0[1] integrating input a = analog, i = input, o = output, oh = 5 ma high output drive note 1. these are the issp pins, that are not high z at por (power on reset). refer the psoc programmable system-on-chip technical reference manual for details.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 8 of 41 24-pin part pinout figure 4. cy8c20324 24-pin psoc device qfn (top view) ai, p2[5] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2], ai p0[0], ai 24 23 22 21 20 19 p0[3], ai p0[5], ai p0[7], ai vdd p0[4], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, data*, i2c sda, p1[0] ai, p1[2] ai, p2[3] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[0], ai p0[6], ai ai, clk*, i2c scl p0[1], ai vss notes 2. the center pad on the qfn package is connected to ground (v ss ) for best mechanical, thermal, and electrical performanc e. if not connected to ground, it is electrically floated and not connected to any other signal. 3. these are the issp pins, that are not high z at por (power on reset). refer the psoc programmable system-on-chip technical reference manual for details. table 2. 24-pin part pinout (qfn [2] ) pin no. digital analog name description 1 i/o i p2[5] 2 i/o i p2[3] 3 i/o i p2[1] 4 i oh i p1[7] i 2 c scl, spi ss 5 i oh i p1[5] i 2 c sda, spi miso 6 i oh i p1[3] spi clk 7 i oh i p1[1] clk [3] , i 2 c scl, spi mosi 8 nc no connection 9 power v ss ground connection 10 i oh i p1[0] data [3] , i 2 c sda 11 i oh i p1[2] 12 i oh i p1[4] optional external clock input (extclk) 13 i oh i p1[6] 14 input xres active high external reset with internal pull-down 15 i/o i p2[0] 16 i/o i p0[0] 17 i/o i p0[2] 18 i/o i p0[4] 19 i/o i p0[6] 20 power v dd supply voltage 21 i/o i p0[7] 22 i/o i p0[5] 23 i/o i p0[3] integrating input 24 i/o i p0[1] integrating input cp power vss center pad is connected to ground a = analog, i = input, o = output, oh = 5 ma high output drive
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 9 of 41 28-pin part pinout figure 5. cy8c20524 28-pin psoc device table 3. 28-pin part pinout (ssop) pin no. digital analog name description 1 i/o i p0[7] 2 i/o i p0[5] 3 i/o i p0[3] integrating input 4 i/o i p0[1] integrating input 5 i/o i p2[7] 6 i/o i p2[5] 7 i/o i p2[3] 8 i/o i p2[1] 9 power v ss ground connection 10 i oh i p1[7] i 2 c scl, spi ss 11 i oh i p1[5] i 2 c sda, spi miso 12 i oh i p1[3] spi clk 13 i oh i p1[1] clk [4] , i 2 c scl, spl mosi 14 power v ss ground connection 15 i oh i p1[0] data [4] , i 2 c sda 16 i oh i p1[2] 17 i oh i p1[4] optional external clock input (extclk) 18 i oh i p1[6] 19 input xres active high external reset with internal pull-down 20 i/o i p2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 i/o i p0[0] 25 i/o i p0[2] 26 i/o i p0[4] 27 i/o i p0[6] 28 power v dd supply voltage a = analog, i = input, o = output, oh = 5 ma high output drive note 4. these are the issp pins, that are not high z at por (power on reset). refer the psoc programmable system-on-chip technical reference manual for details.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 10 of 41 32-pin part pinout figure 6. cy8c20424 32-pin psoc device ai, p0[1] ai, p2[7] ai, p2[5] ai, p2[3] ai, p2[1] ai, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], ai p0[7], ai vdd p0[6], ai p0[4], ai p0[2], ai ai, p3[1] spi ss, p1[7] p0[0], ai p2[6], ai p3[0], ai xres ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] ai, clk*, i2c scl, spi mosi, p1[1] vss ai, data*, i2c sda, p1[0] ai, p1[2] ai, extclk, p1[4] ai, p1[6] p2[4], ai p2[2], ai p2[0], ai p3[2], ai p0[5], ai ai, i2c sc l notes 5. the center pad on the qfn package is connected to ground (v ss ) for best mechanical, thermal, and electrical perform ance. if not connected to gr ound, it is electrically floated and not connected to any other signal. 6. these are the issp pins, that are not high z at por (power on reset). refer the psoc programmable system-on-chip technical reference manual for details. table 4. 32-pin part pinout (qfn [5] ) pin no. digital analog name description 1 i/o i p0[1] integrating input 2 i/o ip2[7] 3 i/o ip2[5] 4 i/o i p2[3] 5 i/o i p2[1] 6 i/o ip3[3] 7 i/o i p3[1] 8 i oh i p1[7] i 2 c scl, spi ss 9 i oh i p1[5] i 2 c sda, spi miso 10 i oh i p1[3] spi clk 11 i oh i p1[1] clk [6] , i 2 c scl, spi mosi 12 power v ss ground connection 13 i oh i p1[0] data [6] , i 2 c sda 14 i oh i p1[2] 15 i oh i p1[4] optional external clock input (extclk) 16 i oh i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o ip3[0] 19 i/o ip3[2] 20 i/o ip2[0] 21 i/o i p2[2]
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 11 of 41 22 i/o i p2[4] 23 i/o i p2[6] 24 i/o i p0[0] 25 i/o ip0[2] 26 i/o ip0[4] 27 i/o i p0[6] 28 power v dd supply voltage 29 i/o i p0[7] 30 i/o i p0[5] 31 i/o i p0[3] integrating input 32 power v ss ground connection cp power v ss center pad is connected to ground a = analog, i = input, o = output, oh = 5 ma high output drive table 4. 32-pin part pinout (qfn [5] ) (continued) pin no. digital analog name description
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 12 of 41 48-pin ocd part pinout the 48-pin qfn part table and pin diagram is for the cy8c20024 on-chip debug (ocd) psoc device. this part is only used for in-circuit debugging. it is not available for production . figure 7. cy8c20024 ocd psoc device ocd qfn (top view) nc vss p0[3], ai p0[5], ai p0[7], ai ocde ocdo vdd p0[6], ai nc nc nc 10 11 12 nc ai, p0[1] ai, p2[7] ai, p2[5] ai, p2[3] ai, p2[1] ai, p3[3] ai, p3[1] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] nc nc 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p0[2], ai p0[0], ai p2[6], ai p2[4], ai p2[2], ai p2[0], ai p3[2], ai p3[0], ai xres p1[6], ai p1[4], extclk, ai p0[4], ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 nc nc ai, spi clk, p1[3] ai, clk*, i2c scl, spi mosi, p1[1] vss cclk hclk ai, data*, i2c sda, p1[0] ai, p1[2] nc nc nc table 5. 48-pin ocd part pinout (qfn [7] ) pin no. digital analog name description 1 nc no connection 2 i/o i p0[1] integrating input 3 i/o ip2[7] 4 i/o ip2[5] 5 i/o i p2[3] 6 i/o i p2[1] 7 i/o ip3[3] 8 i/o i p3[1] 9 i oh i p1[7] i 2 c scl, spi ss 10 i oh i p1[5] i 2 c sda, spi miso 11 nc no connection 12 nc no connection 13 nc no connection 14 nc no connection 15 i oh i p1[3] spi clk 16 i oh i p1[1] clk [8] , i 2 c scl, spi mosi 17 power vss ground connection 18 cclk ocd cpu clock output 19 hclk ocd high speed clock output 20 i oh i p1[0] data [8] , i 2 c sda notes 7. the center pad on the qfn package is connected to ground (v ss ) for best mechanical, thermal, and electrical perform ance. if not connected to gr ound, it is electrically floated and not connected to any other signal. 8. these are the issp pins, that are not high z at por (power on reset). refer the psoc programmable system-on-chip technical reference manual for details.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 13 of 41 21 i oh i p1[2] 22 nc no connection 23 nc no connection 24 nc no connection 25 i oh i p1[4] optional external clock input (extclk) 26 i oh i p1[6] 27 input xres active high external reset with internal pull-down 28 i/o ip3[0] 29 i/o ip3[2] 30 i/o ip2[0] 31 i/o i p2[2] 32 i/o i p2[4] 33 i/o i p2[6] 34 i/o i p0[0] 35 i/o i p0[2] 36 i/o i p0[4] 37 nc no connection 38 nc no connection 39 nc no connection 40 i/o i p0[6] 41 power v dd supply voltage 42 ocdo ocd odd data output 43 ocde ocd even data i/o 44 i/o i p0[7] 45 i/o i p0[5] 46 i/o i p0[3] integrating input 47 power v ss ground connection 48 nc no connection cp power v ss center pad is connected to ground a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive. table 5. 48-pin ocd part pinout (qfn [7] ) (continued) pin no. digital analog name description
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 14 of 41 electrical specifications this section presents the dc and ac electrical specifications of the cy8c20224, cy8c20324, cy8c20424, and cy8c20524 psoc devices. for the latest electrical specifications, visit the web at http://www.cypress.com/psoc . specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c as specified, except where noted. refer to table 16 on page 19 for the electrical specificat ions on the internal main o scillator (imo) using slimo mode. figure 8. voltage versus cpu frequency and imo frequency trim options absolute maximum ratings operating temperature 5.25 4.75 3.00 750 khz 12 mhz cpu frequency vdd voltage 5.25 4.75 3.00 750 khz 6 mhz 12 mhz imo frequency vdd voltage 3.60 3 mhz 2.40 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 slimo mode=1 slimo mode=0 2.70 slimo mode=1 slimo mode=0 2.70 6 mhz table 6. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduces data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 65 c degrades reliability. t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 7. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see table 31 on page 30 . the user must limit the power consumption to comply with this requirement.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 15 of 41 dc electrical characteristics dc chip level specifications ta b l e 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively . typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. dc gpio specifications unless otherwise noted, ta b l e 9 lists the guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, and 2.7 v at 25 c. these are for design guidance only. table 8. dc chip level specifications symbol description min typ max units notes v dd supply voltage 2.40 ? 5.25 v i dd12 supply current, imo = 12 mhz ? 1.5 2.5 ma conditions are v dd = 3.0 v, t a = 25 c, cpu = 12 mhz. i dd6 supply current, imo = 6 mhz ? 1 1.5 ma conditions are v dd = 3.0 v, t a = 25 c, cpu = 6 mhz. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4 a v dd = 2.55 v, 0 c ?? t a ? 40 c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a v dd = 3.3 v, ?40 c ?? t a ? 85 c. table 9. 5-v and 3.3-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? v oh1 high output voltage port 0, 2, or 3 pins v dd ? 0.2 ? ? v i oh < 10 a, v dd > 3.0 v, maximum of 20 ma source current in all i/os. v oh2 high output voltage port 0, 2, or 3 pins v dd ? 0.9 ? ? v i oh = 1 ma, v dd > 3.0 v, maximum of 20 ma source current in all i/os. v oh3 high output voltage port 1 pins with ldo regulator disabled v dd ? 0.2 ? ? v i oh < 10 a, v dd > 3.0 v, maximum of 10 ma source current in all i/os. v oh4 high output voltage port 1 pins with ldo regulator disabled v dd ? 0.9 ? ? v i oh = 5 ma, v dd > 3.0 v, maximum of 20 ma source current in all i/os. v oh5 high output voltage port 1 pins with 3.0 v ldo regulator enabled 2.7 3.0 3.3 v i oh < 10 a, v dd > 3.1 v, maximum of 4 i/os all sourcing 5 ma. v oh6 high output voltage port 1 pins with 3.0 v ldo regulator enabled 2.2 ? ? v i oh = 5 ma, v dd > 3.1 v, maximum of 20 ma source current in all i/os. v oh7 high output voltage port 1 pins with 2.4 v ldo regulator enabled 2.1 2.4 2.7 v i oh < 10 a, v dd > 3.0 v, maximum of 20 ma source current in all i/os. v oh8 high output voltage port 1 pins with 2.4 v ldo regulator enabled 2.0 ? ? v i oh < 200 a, v dd > 3.0 v, maximum of 20 ma source current in all i/os. v oh9 high output voltage port 1 pins with 1.8 v ldo regulator enabled 1.6 1.8 2.0 v i oh < 10 a 3.0 v ?? v dd ?? 3.6 v 0 c ?? t a ??? 85 c maximum of 20 ma source current in all i/os. v oh10 high output voltage port 1 pins with 1.8 v ldo regulator enabled 1.5 ? ? v i oh < 100 a 3.0 v ?? v dd ?? 3.6 v 0 c ?? ta ??? 85 c maximum of 20 ma source current in all i/os. v ol low output voltage ? ? 0.75 v i ol = 20 ma, v dd > 3.0v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]).
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 16 of 41 i oh2 high level source current port 0, 2, or 3 pins 1 ? ? ma v oh = v dd ? 0.9, for the limitations of the total current and i oh at other v oh levels see the notes for v oh . i oh4 high level source current port 1 pins with ldo regulator disabled 5??mav oh = v dd ? 0.9, for the limitations of the total current and i oh at other v oh levels see the notes for v oh . i ol low level sink current 20 ? ? ma v oh = 0.75 v, see the limitations of the total current in the note for v ol . v il input low voltage ? ? 0.8 v 3.0 v ? v dd ? 5.25 v v ih input high voltage 2.0 ? v 3.0 v ? v dd ? 5.25 v v h input hysteresis voltage ? 140 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent temperature = 25 c c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent temperature = 25 c table 9. 5-v and 3.3-v dc gpio specifications (continued) symbol description min typ max units notes table 10. 2.7-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? v oh1 high output voltage port 1 pins with ldo regulator disabled v dd ? 0.2 ? ? v i oh < 10 a, maximum of 10 ma source current in all i/os. v oh2 high output voltage port 1 pins with ldo regulator disabled v dd ? 0.5 ? ? v i oh = 2 ma, maximum of 10 ma source current in all i/os. v ol low output voltage ? ? 0.75 v i ol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]). i oh2 high level source current port 1 pins with ldo regulator disabled 2??mav oh = v dd ? 0.5, for the limitations of the total current and i oh at other v oh levels see the notes for v oh . i ol low level sink current 10 ? ? ma v oh = 0.75 v, see the limitations of the total current in the note for v ol . v olp1 low output voltage port 1 pins ? ? 0.4 v iol = 5 ma maximum of 50 ma sink current on even port pins (for example, p0[2] and p3[4]) and 50 ma sink current on odd port pins (for example, p0[3] and p2[5]). 2.4 v ? v dd ? 3.0 v v il input low voltage ? ? 0.75 v 2.4 v ? v dd ? 3.0 v v ih1 input high voltage 1.4 ? ? v 2.4 v ? v dd ? 2.7 v v ih2 input high voltage 1.6 ? ? v 2.7 v ? v dd ? 3.0 v v h input hysteresis voltage ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent temperature = 25 c c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent temperature = 25 c
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 17 of 41 dc analog mux bus specifications ta b l e 11 lists the guaranteed maximum and minimum specifications for t he voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. dc low power comparator specifications ta b l e 1 2 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v at 25 c. these are for design guidance only. dc por and lvd specifications ta b l e 1 3 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 11. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 800 ? ? vdd ? 2.7 v 2.4 v ?? vdd ?? 2.7 v table 12. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd ? 1.0 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 13. dc por and lvd specifications symbol description min typ max units notes vppor0 vppor1 vppor2 v dd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.60 2.82 2.40 2.65 2.95 v v v v dd is greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. vlvd0 vlvd1 vlvd2 vlvd3 vlvd4 vlvd5 vlvd6 vlvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.39 2.54 2.75 2.85 2.96 ? ? 4.52 2.45 2.71 2.92 3.02 3.13 ? ? 4.73 2.51 [9] 2.78 [10] 2.99 [11] 3.09 3.20 ? ? 4.83 v v v v v v v v notes 9. always greater than 50 mv above v ppor (porlev = 00) for falling supply. 10. always greater than 50 mv above v ppor (porlev = 01) for falling supply. 11. always greater than 50 mv above v ppor (porlev = 10) for falling supply. 12. a maximum of 36 50,000 block endurance cycles is allowed. this is balanced between opera tions on 36 1 blocks of 50,000 m aximum cycles each, 36 2 blocks of 25,000 maximum cycles each, or 36 4 bl ocks of 12,500 maximum cycles ea ch (to limit the total number of cycles to 36 50,0 00 and that no single block ever sees more than 50,000 cycles). 13. the 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. volta ge ranges are 2.4 v to 3.0 v, 3.0 v to 3.6 v and 4.75 v to 5.25 v.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 18 of 41 dc programming specifications ta b l e 1 4 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. dc i 2 c specifications ta b l e 1 5 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 14. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 2.4 2.5 2.6 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 2.7 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? v ss + 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) [13] 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [12] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years table 15. dc i 2 c specifications [14] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v ?? v dd ? 3.6 v ? ? 0.25 v dd v4.75 v ? v dd ? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v ? v dd ? 5.25 v notes 14. all gpio meet the dc gpio v il and v ih specifications found in the dc gp io specifications sections. the i 2 c gpio pins also meet the above specs . 15. 0 c to 70 c ambient, v dd = 3.3 v.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 19 of 41 ac electrical characteristics ac chip level specifications table 16 and table 17 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ? 40 c ? t a ? 85 c, 3.0 v to 3.6 v and ? 40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ? 40 c ? t a ? 85 c respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 16. 5-v and 3.3-v ac chip-level specifications symbol description min typ max units notes f cpu1 cpu frequency (3.3 v nominal) 0.75 ? 12.6 mhz 12 mhz only for slimo mode = 0 f 32k1 ilo frequency 15 32 64 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. f imo12 imo stability for 12 mhz (commercial temperature) [15] 11.4 12 12.6 mhz trimmed for 3.3 v operation using factory trim values. see figure 8 on page 14 , slimo mode = 0. f imo6 imo stability for 6 mhz (commercial temperature) 5.5 6.0 6.5 mhz trimmed for 3.3 v operation using factory trim values. see figure 8 on page 14 , slimo mode = 1. dc imo duty cycle of imo 40 50 60 % dc ilo ilo duty cycle 20 50 80 % t ramp supply ramp time 0 ? ? s t xrst external reset pulse width 10 ? ? s t powerup time from end of por to cpu executing code ? 16 100 ms power up from 0 v. see the system resets section of the psoc technical reference manual . t jit_imo [16] 12 mhz imo cycle-to-cycle jitter (rms) ? 200 1600 ps 12 mhz imo long term n cycle-to-cycle jitter (rms) ? 600 1400 ps n = 32 12 mhz imo period jitter (rms) ? 100 900 ps table 17. 2.7-v ac chip level specifications symbol description min typ max units notes f cpu1a cpu frequency (2.7 v nominal) 0.75 ? 3.25 mhz 2.4 v < v dd < 3.0 v. f cpu1b cpu frequency (2.7 v minimum) 0.75 ? 6.3 mhz 2.7 v < v dd < 3.0 v. f 32k1 ilo frequency 8 32 96 khz f 32k_u ilo untrimmed frequency 5 ? ? khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. f imo12 imo stability for 12 mhz (commercial temperature) [15] 11.0 12 12.9 mhz trimmed for 2.7 v operation using factory trim values. see figure 8 on page 14 , slimo mode = 0. f imo6 imo stability for 6 mhz (commercial temperature) 5.5 6.0 6.5 mhz trimmed for 2.7 v operation using factory trim values. see figure 8 on page 14 , slimo mode = 1. dc imo duty cycle of imo 40 50 60 % dc ilo ilo duty cycle 20 50 80 % t ramp supply ramp time 0 ? ? s t xrst external reset pulse width 10 ? ? s note 16. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timing products - an5054 for more information
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 20 of 41 ac gpio specifications ta b l e 1 8 an d table 19 list the guaranteed maximum and minimum specificati ons for the voltage and temperature ranges: 4.75 v to 5.25v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. figure 9. gpio timing diagram t powerup ? 16 100 ms power-up from 0 v. see the system resets section of the psoc te c h n i c a l reference manual . t jit_imo [16] 12 mhz imo cycle-to-cycle jitter (rms) ? 500 900 ps 12 mhz imo long term n cycle-to-cycle jitter (rms) ? 800 1400 ps n = 32 12 mhz imo period jitter (rms) ? 300 500 ps table 17. 2.7-v ac chip level specifications (continued) symbol description min typ max units notes table 18. 5 v and 3.3 v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 6 mhz normal strong mode, port 1. t rise023 rise time, strong mode, cload = 50 pf ports 0, 2, 3 15 ? 80 ns v dd = 3.0 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% t rise1 rise time, strong mode, cload = 50 pf port 1 10 ? 50 ns v dd = 3.0 v to 3.6 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf all ports 10 ? 50 ns v dd = 3.0 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% table 19. 2.7 v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 1.5 mhz normal strong mode, port 1. t rise023 rise time, strong mode, cload = 50 pf ports 0, 2, 3 15 ? 100 ns v dd = 2.4 v to 3.0 v, 10% to 90% t rise1 rise time, strong mode, cload = 50 pf port 1 10 ? 70 ns v dd = 2.4 v to 3.0 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf all ports 10 ? 70 ns v dd = 2.4 v to 3.0 v, 10% to 90% tfall trise023 trise1 90% 10% gpio pin output voltage
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 21 of 41 ac comparator specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. ac low power comparator specifications ta b l e 2 1 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v at 25 c. these are for design guidance only. ac external clock specifications ta b l e 2 2 , table 23 , and ta b l e 2 4 list the guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 20. ac comparator specifications symbol description min typ max units notes t comp comparator response time , 50 mv overdrive ? ? 100 200 ns ns v dd ? 3.0 v 2.4 v < v cc < ? 3.0 v table 21. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s ? 50 mv overdrive comparator reference set within v reflpc . table 22. 5 v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.750 ? 12.6 mhz ? high period 38 ? 5300 ns ? low period 38 ? ?ns ? power-up imo to switch 150 ? ?s table 23. 3.3 v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.750 ? 12.6 mhz maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ?s
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 22 of 41 ac programming specifications ta b l e 2 5 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c respectively . typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 24. 2.7 v ac external clock specifications symbol description min typ max units notes f oscext1a frequency with cpu clock divide by 1 (2.7 v nominal) 0.75 ?3.08 0 mhz 2.4 v < v dd < 3.0 v. maximum cpu frequency is 3 mhz at 2.7 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext1b frequency with cpu clock divide by 1 (2.7 v minimum) 0.75 ?6.3 0 mhz 2.7 v < v dd < 3.0 v. maximum cpu frequency is 3 mhz at 2.7 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext2a frequency with cpu clock divide by 2 or greater (2.7 v nominal) 1.5 ?6.35mhz2.4 v < v dd < 3.0 v. if the frequency of the external clock is greater than 3 mhz, the cpu clock divider is set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. f oscext2b frequency with cpu clock divide by 2 or greater (2.7 v minimum) 1.5 ? 12.6 mhz 2.7 v < v dd < 3.0 v. if the frequency of the external clock is greater than 3 mhz, the cpu clock divider is set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power-up imo to switch 150 ? ?s table 25. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns 3.6 ? v dd t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 ? v dd ? 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 ? v dd ? 3.0 t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once t program_hot flash block erase + flash block write time ? ? 100 ms 0 c ? tj ? 100 c t program_cold flash block erase + flash block write time ? ? 200 ms ?40 c ? tj ? 0 c
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 23 of 41 ac i 2 c specifications ta b l e 2 6 and table 27 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 26. ac characteristics of the i 2 c sda and scl pins for v dd ? ? 3.0 v symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ?s t lowi2c low period of the scl clock 4.7 ?1.3 ?s t highi2c high period of the scl clock 4.0 ?0.6 ?s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ?s t hddati2c data hold time 0 ?0 ?s t sudati2c data setup time 250 ? 100 [17] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ?s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ?s t spi2c pulse width of spikes are suppressed by the input filter ? ?050ns table 27. 2.7-v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 ??khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ?s t lowi2c low period of the scl clock 4.7 ? ? ?s t highi2c high period of the scl clock 4.0 ? ? ?s t sustai2c setup time for a repeated start condition 4.7 ? ? ?s t hddati2c data hold time 0 ? ? ?s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ?s t bufi2c bus free time between a stop and start condition 4.7 ?? ?s t spi2c pulse width of spikes are suppressed by the input filter. ? ???ns note 17. a fast mode i 2 c bus device is used in a standard mode i 2 c bus system but the requirement t sudat ? 250 ns is met. this automatically is the case if the device does not stretch the low period of the scl signal. if such device doe s stretch the low period of the scl signal, it must output the next data bit to the sda line trmax + t sudat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 24 of 41 figure 10. definition for timing for fast or standard mode on the i 2 c bus i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 25 of 41 table 28. spi master ac specifications symbol parameter conditions min typ max units f sclk sclk clock frequency ? ? 12 mhz dc sclk duty cycle ? 50 ? % t setup miso to sclk setup time 40 ? ? ns t hold sclk to miso hold time 40 ? ? ns t out_val sclk to mosi valid time ? ? 40 ns t out_h mosi high time 40 ? ? ns table 29. spi slave ac specifications symbol parameter conditions min typ max units f sclk sclk clock frequency ? ? 4 mhz t low sclk low time 41.67 ? ? ns t high sclk high time 41.67 ? ? ns t setup mosi to sclk setup time 30 ? ? ns t hold sclk to mosi hold time 50 ? ? ns t ss_miso ss high to miso valid ? ? 153 ns t sclk_miso sclk to miso valid ? ? 125 ns t ss_high ss high time ? ? 50 ns t ss_clk time from ss low to first sclk 2/sclk ? ? ns t clk_ss time from last sclk to ss high 2/sclk ? ? ns
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 26 of 41 ordering information ta b l e 3 0 lists the cy8c20224, cy8c20324, cy8c20424, and cy8c20524 psoc devices key package features and ordering codes. note for die sales information, contact a local cypress sales office or field applications engineer (fae). ordering code definitions table 30. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) maximum number of buttons maximum number of sliders maximum number of leds configurable led behavior (fade, strobe) proximity sensing 16-pin (3 3 mm 0.60 max) col cy8c20224-12lkxi 8 k 512 10 1 13 yes yes 16-pin (3 3 mm 0.60 max) col (tape and reel) cy8c20224-12lkxit 8 k 512 10 1 13 yes yes 24-pin (4 4 mm 0.60 max) qfn cy8c20324-12lqxi 8 k 512 17 1 20 yes yes 24-pin (4 4 mm 0.60 max) qfn (tape and reel) cy8c20324-12lqxit 8 k 512 17 1 20 yes yes 28-pin (210-mil) ssop CY8C20524-12PVXI 8 k 512 21 1 24 yes yes 28-pin (210-mil) ssop (tape and reel) CY8C20524-12PVXIt 8 k 512 21 1 24 yes yes 32-pin (5 5 mm 0.60 max) qfn (sawn) cy8c20424-12lqxi 8 k 512 25 1 28 yes yes 32-pin (5 5 mm 0.60 max) qfn (sawn) cy8c20424-12lqxit 8 k 512 25 1 28 yes yes cy 8 c 20 xxx - 12 xx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx/lqx = qfn pb-free ax = tqfp pb-free speed: 12 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 27 of 41 packaging dimensions this section illustrates the packaging specifications for th e cy8c20224, cy8c20324, cy8c20424, and cy8c20524 psoc devices, along with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a det ailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . figure 11. 16-pin (3 3 mm 0.6 max) col 001-09116 *f
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 28 of 41 figure 12. 24-pin (4 4 0.6 mm) qfn figure 13. 28-pin (210-mil) ssop 001-13937 *d 51-85079 *e
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 29 of 41 figure 14. 32-pin (5 5 0.60 max) qfn (sawn) figure 15. 48-pin (7 7 mm) qfn important for information on the preferred dimensions for mounti ng the qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf. it is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin qfn psoc devices. 001-48913 *b 001-12919 *c
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 30 of 41 thermal impedances solder reflow specifications ta b l e 3 2 lists the minimum solder reflow peak temperature to achieve good solderability. table 31. thermal impedances per package package typical ? ja [18] 16-pin col 46 c/w 24-pin qfn [19] 25 c/w 28-pin ssop 96 c/w 32-pin qfn [19] 27 c/w 48-pin qfn [19] 28 c/w table 32. solder reflow specifications package maximum peak temperature time at maximum peak temperature 16-pin col 260 c 30 s 24-pin qfn 260 c 30 s 28-pin ssop 260 c 30 s 32-pin qfn 260 c 30 s 48-pin qfn 260 c 30 s notes 18. t j = t a + power x ? ja. 19. to achieve the thermal impedance specified for the qfn package , the center thermal pad is soldered to the pcb ground plane.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 31 of 41 development tool selection software psoc designer at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for over half a decade. psoc designer is available free of charge at http://www.cypress.com . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice- cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer supports the advan ce emulation features also. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable two cy8c29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools are sold at the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping prog rammer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiomete r, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a development board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of bread b oarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 32 of 41 device programmers all device programmers are purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs s pecial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) third party tools several tools are specially designed by the following third party vendors to accompany psoc devices during development and production. specific details of each of these tools are found at http://www.cypress.com under design resources >> evaluation boards. build a psoc emulator into your board for details on emulating the circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, refer application note an2323 ?build a psoc emulator into your board?. table 33. emulation and programming accessories part number pin package flex-pod kit [20] foot kit [21] prototyping module adapter [22] cy8c20224-12lkxi 16-pin col not available not available cy3210-20x34 - cy8c20324-12lqxi 24-pin qfn cy3250-20334qfn cy 3250-24qfn-fk cy3210-2 0x34 as-24-28-01ml-6 CY8C20524-12PVXI 28-pin ssop cy3250-20 534 cy3250-28ssop-fk cy3210-20x34 - notes 20. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 21. foot kit includes surface mount feet that is soldered to the target pcb. 22. programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the ada pters is found at http://www.emulation.com .
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 33 of 41 acronyms acronyms used ta b l e 3 4 lists the acronyms that are used in this document. reference documents psoc ? cy8c20x34 and psoc ? cy8c20x24 technical reference manual (trm) ? 001-13033 design aids ? reading and writing psoc ? flash ? an2015 (001-40459) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 34. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter ocd on-chip debug api application programming interface pcb printed circuit board cmos complementary metal oxide semiconductor pga programmable gain amplifier cpu central processing unit por power on reset eeprom electrically erasable programmable read-only memory ppor precision power on reset gpio general purpose i/o psoc? programmable system-on-chip ice in-circuit emulator pwm pulse width modulator idac current dac qfn quad flat no leads ide integrated development environment slimo slow imo ilo internal low speed oscillator spi tm serial peripheral interface imo internal main oscillator sram static random access memory i/o input/output srom supervisory read only memory issp in-system serial programming ssop shrink small-outline package lcd liquid crystal display usb universal serial bus ldo wdt watchdog timer led light-emitting diode wlcsp wafer level chip scale package lvd low voltage detect xres external reset mcu microcontroller unit
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 34 of 41 document conventions units of measure ta b l e 3 5 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 35. units of measure symbol unit of measure symbol unit of measure c degree celsius ms millisecond pf picofarad ns nanosecond khz kilohertz ps picosecond mhz megahertz v microvolts k ? kilohm mv millivolts ? ohm v volts a microampere w watt ma milliampere mm millimeter na nanoampere % percent s microsecond glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device.
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 35 of 41 block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. glossary (continued)
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 36 of 41 emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . glossary (continued)
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 37 of 41 microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memo ry, timing circuits, and i/o circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the vo ltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. glossary (continued)
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 38 of 41 settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued)
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 39 of 41 document history page document title: cy8c20224, cy8c20324, cy8c20424, cy8c20524 capsense ? psoc ? programmable system-on-chip? document number: 001-41947 revision ecn orig. of change submission date description of change ** 1734104 yhw/aesa see ecn new parts and document (revision **). *a 2542938 rlrm/aesa 07/28/2008 corrected ordering information format. updated package diagram 001-13937 to rev *b. updated data sheet template. *b 2610469 snv/pyrs 11/20/08 updated v oh5 , v oh7 , and v oh9 specifications. *c 2634376 drsw 01/12/09 removed the part number cy3250-20234qfn from the 'cy8c20224-12lkxi' flex-pod kit changed title from capsense? multimedia psoc ? mixed-signal array to capsense? multimedia psoc ? programmable system-on-chip? added -12 to the cy8c20524 parts in the ordering information table updated ?development tools? and ?designing with psoc designer? sections on pages 4 and 5 updated ?development tools selection? section on page 30 changed status from ?preliminary? to ?final? changed 16-pin from qfn to col *d 2693024 dpt/pyrs 04/16/2009 added 32-pin sawn qfn package diagram added devices cy8c20424-12lqxi and cy8c20424-12lqxit in the ordering information table *e 2717566 drsw/aesa 06/11/2009 updated ac chip-level, and ac programming specifications as follows: modified fimo6 (page 19), twrite specifications (page 22) added ioh & iol (page 16), flash endurance note (page 18), dcilo (page 19), f32k_u (page 19), tpowerup (page 19), teraseall (page 22), tprogram_hot (page 22), and tprogram_cold (page 22) specifications added ac spi master and slave specifications *f 2899195 cfw/isw 03/26/2010 updated package diagrams updated ordering information *g 3037121 cfw 09/24/2010 updated title to read ac comparator specifications and also updated table caption to read ?ac comparator specifications? in the same section. minor edits and updated in new template. *h 3049675 btk 10/06/2010 removed ac analog mux bus specifications. updated development tools and designing with psoc designer sections. *i 3072668 njf 10/27/10 added psoc device characteristics table. added dc i 2 c specifications table. added f 32k_u max limit. added tjit_imo specification, remov ed existing jitter specifications. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changed were made to i 2 c timing diagram. updated for clearer understanding. template and styles update. *j 3112469 arvm 12/16/10 removed pruned part cy8c20424-12lkxit from the ordering information table. *k 3182773 matt 03/01/11 no change
cy8c20224, cy8c20324 cy8c20424, cy8c20524 document number: 001-41947 rev. *l page 40 of 41 *l 3638597 bvi 06/06/2012 updated getting started section. updated software under development tool selection section. updated solder reflow specifications table. updated f sclk parameter in the table 29, ?spi slave ac specifications,? on page 25. changed t out_high to t out_h in table 28, ?spi master ac specifications,? on page 25 updated package diagrams: 001-09116 to *f 001-13937 to *d 51-85079 to *e 001-12919 to *c removed references to obsolete specs 001-17397 and 001-14503 in page 33. document title: cy8c20224, cy8c20324, cy8c20424, cy8c20524 capsense ? psoc ? programmable system-on-chip? document number: 001-41947
document number: 001-41947 rev. *l revised june 15, 2012 page 41 of 41 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20224, cy8c20324 cy8c20424, cy8c20524 ? cypress semiconductor corporation, 2008-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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